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rt8015 1 ds8015-03 march 2011 www.richtek.com applications l portable instruments l battery-powered equipment l notebook computers l distributed power systems l ip phones l digital cameras general description the rt8015 is a high efficiency synchronous, step-down dc/dc converter. its input voltage range is from 2.6v to 5.5v and provides an adjustable regulated output voltage from 0.8v to 5v while delivering up to 2a of output current. the internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an external schottky diode. switching frequency is set by an external resistor or can be synchronized to an external clock. 100% duty cycle provides low dropout operation extending battery life in portable systems. current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. rt8015 operation in forced continuous pwm mode which minimizes ripple voltage and reduces the noise and rf interference. 100% duty cycle in low dropout operation further maximize battery life. ordering information pin configurations (top view) 2a, 2mhz, synchronous step-down regulator sop-8 (exposed pad) note : richtek products are : } rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. } suitable for use in snpb or pb-free soldering processes. features l high efficiency : up to 95% l low r ds(on) internal switches : 110m w l programmable frequency : 300khz to 2mhz l no schottky diode required l 0.8v reference allows low output voltage l forced continuous mode operation l low dropout operation : 100% duty cycle l rohs compliant and 100% lead (pb)-free shdn/rt gnd lx pgnd comp fb pvdd vdd gnd 2 3 4 5 6 7 8 9 package type sp : sop-8 (exposed pad-option 2) rt8015 lead plating system p : pb free g : green (halogen free and pb free)
rt8015 2 ds8015-03 march 2011 www.richtek.com functional pin description pin no. pin n ame pin function 1 shdn/rt oscillator resistor input. connecting a resistor to ground from this pin sets the switching frequency. forcing this pin to v dd causes the device to be shut down. 2, 9 (exposed pad) gnd signal ground. all small-signal components and compensation components should connect to this ground, which in turn connects to pgnd at one point. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 3 lx internal power mosfet switches output. connect this pin to the inductor. 4 pgnd power ground. connect this pin close to the ( ? ) terminal of c in and c out . 5 pvdd power input supply. decouple this pin to pgnd with a capacitor. 6 vdd signal input supply. decouple this pin to gnd with a capacitor. normally v dd is equal to pvdd. 7 fb feedback pin. receives the feedback voltage from a resistive divider connected across the output. 8 comp error amplifier compensation point. the current comparator threshold increases with this control voltage. connect external compensation elements to this pin to stabilize the control loop. typical application circuit note : using all ceramic capacitors v out l1 (uh) c out (uf) r1 (k ) r2 (k ) r comp (k ) c comp (nf) 3.3v 2.2 22 750 240 13 1 2.5v 2.2 22 510 240 13 1 1.8v 1.0 22 300 240 7.5 1.5 1.2v 1.0 22 120 240 7.5 1.5 recommended component for different output voltage applications 6 vdd pvdd 5 rt8015 v in 2.6v to 5.5v 4 pgnd shdn/rt 1 lx 3 comp fb 7 8 gnd 2, exposed pad (9) r osc 332k c in 22uf l1 2.2uh r1 510k r2 240k c out 22uf r comp 13k c comp 1nf v out 2.5v/2a
rt8015 3 ds8015-03 march 2011 www.richtek.com function block diagram driver nisen control logic nmos i limit 0.9v 0.7v 0.4v oc limit isen slope com osc output clamp ea 0.8v int-ss por otp v ref comp shdn/rt gnd fb pvdd vdd pgnd sd lx
rt8015 4 ds8015-03 march 2011 www.richtek.com operation main control loop the rt8015 is a monolithic, constant-frequency, current mode step-down dc/dc converter. during normal operation, the internal top power switch (p-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the peak inductor current reach the value defined by the voltage on the comp pin. the error amplifier adjusts the voltage on the comp pin by comparing the feedback signal from a resistor divider on the fb pin with an internal 0.8v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error amplifier raises the comp voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-channel mosfet) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. the operating frequency is set by an external resistor connected between the rt pin and ground. the practical switching frequency can range from 300khz to 2mhz. power good comparators will pull the pgood output low if the output voltage comes out of regulation by 12.5%. in an over-voltage condition, the top power mosfet is turned off and the bottom power mosfet is switched on until either the over-voltage condition clears or the bottom mosfet's current limit is reached. frequency synchronization the internal oscillator of the rt8011 can be synchronized to an external clock connected to the sync pin. the frequency of the external clock can be in the range of 300khz to 2mhz. for this application, the oscillator timing resistor should be chosen to correspond to a frequency that is about 20% lower than the synchronization frequency. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the rt8015 is designed to operate down to an input supply voltage of 2.6v. one important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the rt8015 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal. normally, the maximum inductor peak current is reduced when slope compensation is added. in the rt8015, however, separated inductor current signals are used to monitor over current condition. this keeps the maximum output current relatively constant regardless of duty cycle. short circuit protection when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. a current runaway detector is used to monitor inductor current. as current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring.
rt8015 5 ds8015-03 march 2011 www.richtek.com absolute maximum ratings (note 1) l supply input voltage, vdd, pvdd--------------------------------------------------------------------------- - 0.3v to 6v l lx pin switch voltage------------------------------------------------------------------------------------------ - 0.3v to (pvdd + 0.3v) l other i/o pin voltages------------------------------------------------------------------------------------------ - 0.3v to (vdd + 0.3v) l lx pin switch current-------------------------------------------------------------------------------------------4a l power dissipation, p d @ t a = 25 c sop-8 (exposed pad)-----------------------------------------------------------------------------------------1.33w l package thermal resistance (note 2) sop-8 (exposed pad), q ja ------------------------------------------------------------------------------------75 c/w sop-8 (exposed pad), q jc ------------------------------------------------------------------------------------15 c/w l junction temperature-------------------------------------------------------------------------------------------150 c l lead temperature (soldering, 10 sec.)----------------------------------------------------------------------260 c l storage temperature range----------------------------------------------------------------------------------- - 65 c to 150 c l esd susceptibility (note 3) hbm (human body mode)-------------------------------------------------------------------------------------2kv mm (machine mode)--------------------------------------------------------------------------------------------200v electrical characteristics (v dd = 3.3v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit input voltage range v dd 2.6 -- 5.5 v feedback reference voltage v ref 0.784 0.8 0.816 v active , v fb = 0.78v, not switching -- 460 -- m a dc bias current shutdown -- -- 1 m a output voltage line regulation v in = 2.7v to 5.5v -- 0.04 -- %/v output voltage load regulation 0a < i load < 2a -- 0.25 -- % error amplifier transconductance g m -- 800 -- us current sense transresistance r t -- 0.4 -- w power good range -- 12.5 15 % power good pull-down resistance -- -- 120 w r osc = 332k 0.8 1 1.2 mhz switching frequency switching frequency 0.3 -- 2 mhz sync frequency range 0.3 -- 2 mhz to be continued recommended operating conditions (note 4) l supply input voltage--------------------------------------------------------------------------------------------2.6v to 5.5v l junction temperature range---------------------------------------------------------------------------------- - 40 c to 125 c l ambient temperature range---------------------------------------------------------------------------------- - 40 c to 85 c
rt8015 6 ds8015-03 march 2011 www.richtek.com note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. q ja is measured in the natural convection at t a = 25 c on 4-layers high effective thermal conductivity test board of jedec 51-7 thermal measurement standard. the case point of q jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit switch on resistance, high r pmos i sw = 0.5a -- 110 160 m w switch on resistance, low r nmos i sw = 0.5a -- 110 170 m w peak current limit i lim 2.2 3.2 -- a v dd rising -- 2.4 -- v under voltage lockout threshold v dd falling -- 2.3 -- v shutdown threshold v shdn/rt -- v in - 0.7 v in - 0.4 v
rt8015 7 ds8015-03 march 2011 www.richtek.com frequency vs. temperature 1000 1020 1040 1060 1080 1100 -50 -25 0 25 50 75 100 125 temperature frequency (khz) ( c) v in = 3.3v, v out = 1.8v i out = 0a quiescent current vs. input voltage 450 470 490 510 530 550 3 3.253.5 3.75 4 4.254.54.75 5 5.255.5 input voltage (v) quiescent current (ua) quiescent current vs. temperature 400 420 440 460 480 500 -50 -25 0 25 50 75 100 125 temperature quiescent current (ua) ( c) v in = 3.3v peak current limited vs. input voltage 2.0 2.5 3.0 3.5 4.0 3 3.253.5 3.75 4 4.254.54.75 5 5.255.5 input voltage (v) peak current limited (a) v out = 2.5v typical operating characteristics output voltage vs. output current 1.790 1.792 1.794 1.796 1.798 1.800 1.802 1.804 1.806 1.808 1.810 0 250 500 750 1000 1250 15001750 2000 output current (ma) output voltage (v) v in = 3.3v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 250 500 750 100012501500 17502000 output current (ma) efficiency (%) v in = 3.3v, v out = 1.8v v in = 5v, v out = 1.8v
rt8015 8 ds8015-03 march 2011 www.richtek.com v ref vs. input voltage 0.800 0.801 0.802 0.803 0.804 0.805 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 input voltage (v) v ref (v) output ripple time (250ns/div) i lx (2a/div) v out (10mv/div) v in = 5v, v out = 2.5v i out = 2a v lx (5v/div) output ripple time (250ns/div) i lx (2a/div) v out (10mv/div) v in = 3.3v, v out = 2.5v i out = 2a v lx (5v/div) load transient response time (50 s/div) i lx (1a/div) v out (50mv/div) v in = 3.3v, v out = 2.5v i out = 1a to 2a load transient response time (50 s/div) i lx (1a/div) v out (50mv/div) v in = 3.3v, v out = 2.5v i out = 0a to 2a output voltage vs. temperature 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 -50 -25 0 25 50 75 100 125 temperature output voltage (v) ( c) v in = 3.3v
rt8015 9 ds8015-03 march 2011 www.richtek.com soft start and inrush current time (2.5ms/div) i in (2a/div) v lx (5v/div) v in = 5v, v out = 2.5v i out = 2a v out (2v/div) v in (2v/div) soft start and inrush current time (2.5ms/div) i in (2a/div) v lx (5v/div) v in = 3.3v, v out = 2.5v i out = 2a v out (2v/div) v in (2v/div) power on & inductor current time (1ms/div) i lx (2a/div) v lx (5v/div) v in = 3.3v, v out = 2.5v i out = 2a v out (2v/div) v in (2v/div) power good time (1ms/div) i lx (2a/div) v out (2v/div) v in = 3.3v, v out = 2.5v i out = 2a pgood (2v/div) v in (2v/div) power on & inductor current time (1ms/div) i lx (2a/div) v lx (5v/div) v in = 5v, v out = 2.5v i out = 2a v out (2v/div) v in (2v/div)
rt8015 10 ds8015-03 march 2011 www.richtek.com application information the basic rt8015 application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. the operating frequency of the rt8015 is determined by an external resistor that is connected between the rt pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. the rt resistor value can be determined by examining the frequency vs. rt curve. although frequencies as high as 4mhz are possible, the minimum on-time of the rt8015 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 110ns. therefore, the minimum duty cycle is equal to 100 x 110ns x f(hz). inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current d i l increases with higher v in and decreases with higher inductance. having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is d i = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : ? ? - ? ? = d in out out l v v 1 l f v i ? ? - ? ? d = in(max) out l(max) out v v 1 i f v l inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard , which means that inductance collapses abruptly when the peak design current is exceeded. this result in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! the transition from low current operation begins when the peak inductor current falls below the minimum peak current. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in efficiency in the upper range of low current operation. figure 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 100200300400500600700800900100 0 r rt (k ) frequency (mhz) r rt (k w ) 1000 rt = 154k for 2mhz rt = 332k for 1mhz
rt8015 11 ds8015-03 march 2011 www.richtek.com figure 2. setting the output voltage ? ? ? ? + = r2 r1 1 v v ref out using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. output voltage programming the output voltage is set by an external resistive divider according to the following equation : where v ref equals to 0.8v typical. the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 2. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, d v out , is determined by : the output ripple is highest at maximum input voltage since d i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only 1 v v v v i i out in in out out(max) rms - = ? ? + d d out l out 8fc 1 esr i v use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs. size requirements and any radiated field/emi requirements. rt8015 fb gnd v out r1 r2
rt8015 12 ds8015-03 march 2011 www.richtek.com efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as : efficiency = 100% - (l1+ l2+ l3+ ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v dd quiescent current and i 2 r losses. the v dd quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the v dd quiescent current is due to two components : the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge d q moves from v dd to ground. the resulting d q/ d t is the current out of v dd that is typically larger than the dc bias current. in continuous mode, i gatechg = f(qt+qb) where qt and qb are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v dd and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, rsw and external inductor rl. in continuous mode the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the lx pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (d) as follows : rsw = r ds(on) top x d + r ds(on) bot x (1"d) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add rsw to rl and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to d i load(esr) , where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the comp pin external components and output capacitor shown in typical application circuit will provide adequate compensation for most applications. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature 125 c. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junctions to ambient. the maximum power dissipation can be calculated by following formula: p d(max) = ( t j(max) - t a ) / q ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the q ja is the junction to ambient thermal resistance. for recommended operating conditions specification of rt8015, where t j(max) is the maximum junction temperature of the die (125 c) and t a is the maximum ambient temperature. the junction to ambient thermal resistance for sop-8 (exposed pad) package is 75 c/w on the standard jedec 51-7 (4 layers, 2s2p) thermal test board. the copper thickness is 2oz. the maximum power dissipation at t a = 25 c can be calculated by following formula: p d (max) = (125 c - 25 c) / (75 c/w) = 1.33w (sop-8 exposed pad on the minimum layout)
rt8015 13 ds8015-03 march 2011 www.richtek.com the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance q ja . for rt8015 package, the figure 3 of de- rating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. the thermal resistance q ja of sop-8 (exposed pad) is determined by the package design and the pcb design. however, the package design had been designed. if possible, it s useful to increase thermal performance by the pcb design. the thermal resistance q ja can be decreased by adding a copper under the exposed pad of sop-8 (exposed pad) package. as shown in figure 4, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard sop-8 (exposed pad) pad (figure 4.a), q ja is 75 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 4.b) reduces the q ja to 64 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 4.e) reduces the q ja to 49 c/w. figure 3. derating curve for package (b) copper area = 10mm 2 , q ja = 64 c/w (c) copper area = 30mm 2 , q ja = 54 c/w (a) copper area = (2.3 x 2.3) mm 2 , q ja = 75 c/w figure 4. thermal resistance vs. copper area layout thermal design (d) copper area = 50mm 2 , q ja = 51 c/w (e) copper area = 70mm 2 , q ja = 49 c/w 0 0.4 0.8 1.2 1.6 2 2.4 0 20 40 60 80 100 120 140 ambient temperature ( c) power dissipation (w) copper area 70mm 2 50mm 2 30mm 2 10mm 2 min. layout ( c)
rt8015 14 ds8015-03 march 2011 www.richtek.com table 1. recommended inductor table 2. recommended capacitor layout considerations follow the pcb layout guidelines for optimal performance of rt8015. } a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the gnd pin at one point that is then connected to the pgnd pin close to the ic. the exposed pad should be connected to gnd. } connect the terminal of the input capacitor(s), c in , as close as possible to the pvdd pin. this capacitor provides the ac current into the internal power mosfets. } lx node is with high frequency voltage swing and should be kept small area. keep all sensitive small-signal nodes away from lx node to prevent stray capacitive noise pick-up. } flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (pvdd, vdd, vout, pgnd, gnd, or any other dc rail in your system). } connect the fb pin directly to the feedback resistors. the resistor divider must be connected between vout and gnd. figure 5 component supplier series inductance (uh) dcr (m w ) current rating (ma) dimensions (mm) taiyo yuden nr 4018 2.2 60 2700 4.00 x 4.00 x 1.80 sumida cdrh4d28 2.2 31.3 2040 4.50 x 4.50 x 3.00 gotrend gtsd53 2.2 29 2410 5.00x 5.00 x 2.80 taiyo yuden nr 4018 1.0 30 4000 4.00 x 4.00 x 1.80 sumida cdrh4d28c/ld 1.0 17.5 3000 4.50 x 4.50 x 3.00 gotrend gtsd53 1.0 15 4000 5.00x 5.00 x 2.80 component supplier part no. capacitance (uf) case size tdk c3225x5r0j226m 22 1210 tdk c3225x5r0j226m 22 1210 panasonic ecj4yb0j226m 22 1210 panasonic ecj4yb1a226m 22 1210 taiyo yuden LMK325BJ226ML 22 1210 taiyo yuden jmk316bj226ml 22 1206 v in gnd l1 v out gnd c in c out v out r comp c comp r2 r1 c f r osc c in must be placed between v dd and gnd as closer as possible lx should be connected to inductor by wide and short trace, keep sensitive compontents away from this trace output capacitor must be near rt8015 connect the fb pin directly to feedback resistors. the resistor divider must be connected between v out and gnd. comp vdd shdn/rt lx gnd fb pgnd pvdd 4 5 6 3 2 8 7 1 rt8015
rt8015 15 ds8015-03 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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